library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity InputBlock is
  Port (PixelClk : in std_logic;
        RowClk : in std_logic;
        RowEN : in std_logic;
        VSync : in std_logic;
        Reset : in std_logic;
        Data : in std_logic_vector(15 downto 0);
        
        FPGAClk : in std_logic;
        Pixel : out std_logic_vector(15 downto 0);
        HSync : out std_logic;
        VertSync : out std_logic);
end InputBlock;

architecture beh of InputBlock is

  type states is (Calibrate,ImageStart,VertBlank,ImageRec,ImageDone,
                  RowStart,HorizBlank,RowRec,RowDone,
                  ColStart,ColRec,ColDone);
  
  signal cs : states:=Calibrate;
  
  signal PClkEdge : std_logic_vector(1 downto 0):="00";
  signal prevPClk : std_logic:='0';
  signal PClkRisingEdge,PClkFallingEdge : std_logic:='0';

begin
  
  --Pixel Clock Edge Detector
  process(PixelClk,FPGAClk)
  begin
    if rising_edge(FPGAClk) then
	    PClkEdge<=PClkEdge(0) & PixelClk;
		  if PClkEdge = "00" and prevPClk = '1' then
		    PClkFallingEdge <= '1';
    		  PClkRisingEdge<='0';
		    prevPClk<='0';
    		elsif PClkEdge = "11" and prevPClk = '0' then
    		  prevPClk<='1';
		    PClkFallingEdge<='0';
     	  PClkRisingEdge<='1';
     	else
		    PClkFallingEdge<='0';
		    PClkRisingEdge<='0';
    		end if;
  	 end if;
  end process;
  
  --Image State Machine
  process(FPGAClk)
  begin
    if rising_edge(FPGAClk) then
      case cs is
        when Calibrate => null;
        when ImageStart => null;
        when VertBlank => null;
        when ImageRec => null;
        when ImageDone => null;
        when others => null;
      end case;
    end if;
  end process;
  
  --Row State Machine
  process(FPGAClk)
  begin
    if rising_edge(FPGAClk) then
      case cs is
        when RowStart => null;
        when HorizBlank => null;
        when RowRec => null;
        when RowDone => null;
        when others => null;
      end case;
    end if;
  end process;
  
  --Column State Machine
  process(FPGAClk)
  begin
    if rising_edge(FPGAClk) then
      case cs is
        when ColStart => null;
        when ColRec => null;
        when ColDone => null;
        when others => null;
      end case;
    end if;
  end process;
  
end beh;